1. Field of the Invention
The present invention relates, in general, to a method of manufacturing a semiconductor device, and more particularly to a method of forming a contact of a semiconductor device, which overcomes a number of problems encountered in semiconductor devices made from conventional SAC (self-aligned contact) process when forming an electrical contact.
2. Description of the Related Art
In a semiconductor memory device, such as in a DRAM device, an electrical connection between a capacitor and a bit line is often times implemented through a landing plug contact, a bit line contact and a storage node contact. These contact plugs are conventionally constructed by forming an interlayer insulation layer after forming gate lines or bit lines on a substrate, selectively etching the specific portion of the interlayer insulation layer which exists in each contact forming region, depositing a conductive layer, and finally implementing a SAC (self-aligned contact) process using chemically-mechanically polishing (hereinafter referred to as “CMPing”) onto the resultant structure. Usually the objective of CMPing the resultant structure is to remove a portion of the conductive layer which exists on top of the interlayer insulation layer and to remove a predetermined portion of each gate line or bit line hard mask nitride layer so that any adjacent electrical connections are completely isolated from one another.
FIGS. 1A through 1F depict stylized cross-sectional views that illustrate some of the more common semiconductor manufacturing process steps encountered in conventional methods when forming landing plug electrical contacts.
Referring to FIG. 1A, a silicon substrate 1, in which active regions are delimited by a device isolation layer (not shown), is provided. A plurality of gate lines 5 are formed on the silicon substrate 1, in which each gate line 5 comprises a sequentially stacked structure composed of a gate insulation layer 2, a gate conductive layer 3 and a gate line hard mask nitride layer 4. Next, junction regions 6 are formed in the surface of the silicon substrate 1 along both sides of each gate line 5 by way of any number of ion implantation processes. Thereafter, a first spacer nitride layer 7 and a first interlayer insulation layer 8 are sequentially formed over the surface of the resultant silicon substrate 1 which results in covering the gate lines 5 and the junction regions 6.
Referring now to FIG. 1B, subsequent to CMPing the prior art structure depicted in FIG. 1a, a portion of the first interlayer insulation layer 8 and a portion of the first spacer nitride layer 7 are removed until a portion of the gate line hard mask nitride layers 4 is exposed.
Referring now to FIG. 1C, subsequent to forming a polysilicon layer (not shown) on top of a substantial portion of (i) the first interlayer insulation layer 8, (ii) the first spacer nitride layer 7 and (iii) the gate line hard mask nitride layer 4, a first polysilicon hard mask 9 is formed by patterning the polysilicon layer (not shown) to expose selected regions of (i) the first interlayer insulation layer 8, (ii) the gate lines 5, i.e., selected portions of the gate line hard mask nitride layer 4 and (iii) the first spacer nitride layer 7 in which these exposed regions define the active region, i.e., the region not covered by the first polysilicon hard mask.
Referring now to FIG. 2 which depicts a plan top view corresponding to FIG. 1C defined by line 1C-1C′ in FIG. 2. As can be seen from FIG. 2, the first polysilicon hard mask 9 can be formed in such a way as to eventually be able to expose selected portions of the gate lines 5 as well as expose selected portions of the junction regions 6 that are located in the active regions, i.e., the active regions are those regions not covered by the first polysilicon hard mask 9.
Referring now to FIG. 1D, portions of the first interlayer insulation layer 8 are shown etched away which results in forming contact holes 11 for use in exposing portions of the underlying the gate lines 5 and the junction regions 6 through the first polysilicon hard mask 9. That is, by depositing a USG (undoped silicate glass) oxide layer 10 acting as a physical barrier, i.e., a buffer, and performing an etch-back process on the resultant structure 1, contact forming regions, that is, contact holes 11 can be made for use in exposing portions of the gate lines 5 and the underlying junction regions 6.
Referring now to FIG. 1E, next a first polysilicon layer 12 is usually deposed onto the resultant substrate 1 depicted in FIG. 1D. This first polysilicon layer 12 is usually designed to be a conductive layer for the eventual use as an electrical pathway.
Referring now to FIG. 1F, the first polysilicon layer 12, the USG oxide layer 10 acting as the buffer, and the first polysilicon hard mask 9 deposited on the resultant substrate, depicted in FIG. 1E, are then usually CMPed until a portion of the gate line hard mask nitride layer 4 is exposed. As a result, landing plug contacts 12a are formed on the exposed junction regions 6 situated between the exposed gate lines 5.
FIGS. 3A through 3E depict stylized cross-sectional views illustrating some of the more common process steps encountered when using conventional method for use in forming a storage node contact 21a. 
Referring now to FIG. 3a, a silicon substrate 1 is shown having a number of landing plug contacts 12a which are formed through a first interlayer insulation layer 8. Also shown is an insulation layer 13 formed on top of both the landing plug contacts 12a and the first interlayer insulation layer 8. A plurality of bit lines 17 are shown formed on top of the insulation layer 13. Each bit line 17 is shown composed of a barrier layer 14, a conductive layer 15 and a bit line hard mask nitride layer 16 which are sequentially stacked upon one another. A second spacer nitride layer 18 and a second interlayer insulation layer 19 are sequentially formed over the insulation layer 13 and the bit lines 17.
Referring now to FIG. 3b, the second interlayer insulation layer 19 is then usually CMPed to a more planar surface and often times reduced to a predetermined thickness in which the remaining portion of the second interlayer insulation layer 19 is still left covering over the bit lines 17. Subsequent to forming a polysilicon layer (not shown) on top of this remaining portion of the second interlayer insulation layer 19, a second polysilicon hard mask 20 is formed by removing selected areas of the polysilicon layer (not shown) to produce the second polysilicon hard mask 20 which usually delimits the regions in which storage node contacts 21a (not shown) can be formed.
FIG. 4 depicts a stylized top plan view corresponding to FIG. 3B in which is defined by line 3B-3B′ in FIG. 4. As can be readily seen from FIG. 4, the second polysilicon hard masks 20 can be formed in such a way as to expose selected portions of the second interlayer insulation layer 19 in which storage node contacts 21a (not shown) can be formed.
Referring now to FIG. 3C, exposed portions of (i) the second interlayer insulation layer 19, (ii) the second spacer nitride layer 18, (iii) the insulation layer 13, and (iv) the landing plug contacts 12a are shown where the second polysilicon hard mask 20 has been removed as an etch barrier and thus provides the active regions in which the storage node contacts 21a can be eventually formed.
Referring to FIG. 3D, a second polysilicon layer 21 is shown filling in an opened area (not shown) over the silicon substrate 1. This second polysilicon layer 21 can be modified to serve as an electrical conductive material defining a plug (not shown).
Referring now to FIG. 3E, which shows the second polysilicon layer 21 and the second polysilicon hard masks 20 having been CMPed until a portion of the bit line hard mask nitride layer 16 is exposed. As a result, storage node contacts 21a which are formed between the exposed bit lines 17 and which serve as electrical connections to the landing plug contacts 12a. 
One particular problem with conventional methods may occur when forming the landing plug contacts 12a and the storage node contacts 21a is that there results in the unwanted loss of portions of the gate line and the bit line hard mask nitride layers (4 and 16, respectively) when the first and second interlayer insulation layers (8 and 19, respectively) are differentially etched away. Consequently, as shown in FIGS. 5 and 7, an undesirable thickness deviation may result between the opened area and the non-opened area of each of the gate line and bit line hard mask nitride layers (4 and 16, respectively). Due to this fact, when subsequently CMPing the polysilicon layers for plugs in an effort to isolate the landing plug contacts 12a and the storage node contacts 21a, a more homogeneous polishing thickness cannot be achieved.
Moreover, since this undesirable thickness variation of the gate line and bit line hard mask nitride layers (4 and 16, respectively) is dependent upon the opened and non-opened areas on any given wafer circuit design then the polishing thickness must be further increased to assure that complete electrical isolation can be achieved for all of the various electrical contacts throughout the entirety of that given wafer. Therefore, the polishing thicknesses of the CMP process are undesirably increased to prevent the possibility that non-uniformity in the gate line and bit line hard mask nitride layers (4 and 16, respectively) are not shorted.
Referring now to FIG. 6 which are photographs illustrating contact loss difference induced in a wafer after conducting a CMP process for isolating landing plug contacts 12a in the conventional method.
Referring now to FIG. 8 which are photographs illustrating a contact loss difference induced in a wafer after conducting a CMP process for isolating storage node contacts 21a in the conventional method.
Referring now to both to FIGS. 6 and 8, it is to be readily understood that a contact loss difference between the center portion and the peripheral portion of a wafer is substantial. That is to say, the contact loss of the center portion of the wafer is larger than that of the peripheral portion of the wafer.